In recent years, interface circuits for interfacing with other devices (chips) are built into most LSI circuits. In such interface circuits, it is desirable to keep impedance of an output buffer constant, even if elements relating to impedance characteristic of the output buffer, such as process, temperature, or power supply voltage of a semiconductor device, change. If the impedance of the output buffer can be kept constant, delay variations of the output buffer are curtailed, contributing to lowering difficulty of timing design. Thus, there is a large effect with regard to speed improvement in various interface systems. Furthermore, by consistently obtaining a desired impedance, it is possible to curtail excess current, curtailing quantity of generated noise, and enabling a decrease in power consumption.
A semiconductor device provided with an output buffer circuit having this type of impedance adjustment function is disclosed in Patent Document 1. The semiconductor device described in Patent Document 1 is provided with an output buffer having a plurality of PMOS transistors and a plurality of NMOS transistors, a first dummy buffer formed of a plurality of PMOS transistors having a similar configuration to the abovementioned plurality of PMOS transistors, a second dummy buffer formed of a plurality of NMOS transistors having a similar configuration to the abovementioned plurality of NMOS transistors, a first conductivity controller which adjusts a combination of conductivities of the plurality of PMOS transistors forming the first dummy buffer, based on a resistance value of a first reference resistor connected to an external terminal, a second conductivity controller which adjusts a combination of conductivities of the plurality of NMOS transistors forming the second dummy buffer, based on a resistance value of a second reference resistor connected to an external terminal, a first register which registers an adjustment result of the first conductivity controller, and outputs this registered data to the plurality of PMOS transistors of the output buffer, a second register which registers an adjustment result of the second conductivity controller, and outputs this registered data to the plurality of NMOS transistors of the output buffer, and a conductivity period controller which controls conductivity periods of the first dummy buffer and the second dummy buffer, wherein the conductivity period controller makes the first dummy buffer and the second dummy buffer conductive for a period equivalent to a conductivity period of the output buffer.
Furthermore, Patent Document 2 discloses a semiconductor device in which circuit size necessary for a calibration (impedance adjustment) operation of an output circuit and time taken for the calibration operation are reduced. This semiconductor device is provided with a first output buffer which is connected to data pins and is activated at least at data output time, a second output buffer which is connected to the data pins and is activated at least at ODT (On Die Termination) time, and a calibration circuit which is connected to calibration pins and commonly sets impedance of the first and the second output buffers.
[Patent Document 1]
Japanese Patent Kokai Publication P2005-167779A
[Patent Document 2]
Japanese Patent Kokai Publication P2006-203405A